Adata AX2U1066GB1G6-CG Datasheet download pdf

ADQYF1A08_DDR2-1066G(CL=6)_1GB(128Mx8_Pb free) Rev.0 2009/03/30 Page 2 of 7

General Description

The ADATA’s ADQYF1A08 is a 128Mx64 bits 1GB DDR2-1066(CL6) SDRAM over clocking memory module,

The SPD is programmed to JEDEC standard latency 800Mbps timing of 5-5-5-18 at 1.8V. The module is composed

of eight 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP (TSOP)

package on a 240pin glass–epoxy printed circuit board.

The ADQYF1A08 is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector

sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are

possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow

the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features

• Power supply(Normal): VDD & VDDQ = 1.8V ± 0.1V

• 1.8V (SSTL_18 compatible) I/O

• Timing Reference

- DDR2 800 CL5-5-5-18 at 1.8V

- DDR2 1066 CL6-6-6-15 at 2.1V

• Burst Length: 4, 8

• Programmable Additive Latency: 0, 1, 2, 3, 4

• Bi-directional, differential data strobe (DQS and /DQS)

• Differential clock input (CK, /CK) operation

• DLL aligns DQ and DQS transition with CK transition

• Double-data-rate architecture.

• Auto & Self refresh

• Average Refresh period 7.8ȝs

• Off-Chip Driver (OCD) Impedance Adjustment

• On Die Termination (ODT)

• Lead-free products are RoHS compliant

• EEPROM VDDSPD=3.3V (Typical)

• PCB Height 30.00mm (1.181”), Single sided component

• Clock Cycle Time (tCK):

- DDR2-800 tCK=2.5ns

- DDR2-1066 tCK=1.875ns

• Refresh to Active/Refresh Command Time (tRFC): 127.5ns

YF1A08

DDR2-1066G(CL6) 240-Pin O.C. U-DIMM

1GB (128M x 64-bits)

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